Not applicable.
Not applicable.
1. Field of the Invention
The present invention relates generally to computer systems and particularly to power management in a personal computer system. More particularly, the present invention relates to configuring legacy peripheral devices for low-power mode using a software-based power management system.
2. Background of the Invention
Many personal computer systems conserve energy by operating in special low-power modes when the user is not actively using the system. Although used in desktop and portable systems alike, these reduced-power modes particularly benefit laptop and notebook computers by extending the battery life of these systems. Some computer systems automatically enter low-power mode when a user has not performed a certain action within a given period of time. The computer might power down the monitor if the video display has not recently changed, for example, or may power down the hard drive if the user has not recently opened or saved any files onto the hard disk. If the computer detects a period of inactivity, the computer may enter a deep xe2x80x9csleepxe2x80x9d mode in which power is completely cut off to all but a few devices within the computer. In addition, the user often can initiate the sleep mode through a menu in the operating system (OS) or by pressing a power button on the computer. Because the computers random access memory (RAM) remains powered on during sleep mode, the memory contents are preserved so that the computer returns to the same state that it was in when the sleep mode began.
Although these reduced-power modes may render the computer temporarily or partially inoperable, the user can generally restore full-power, or xe2x80x9cwake up,xe2x80x9d the computer at any time. For example, the computer may automatically restore video power if the user moves the mouse or presses a key on the keyboard, or might power up the hard disk if the user attempts to open or save a file. Many computer systems include a power button that the user can press to wake up the machine from sleep mode. In addition, some computers have the capability to wake automatically in response to incoming phone calls detected by a modem or to wakeup messages received over a local area network (LAN). Sleep mode is often an attractive alternative to completely shutting the computer down, because the computer consumes little power during sleep mode and because waking up from sleep mode typically is much faster than rebooting the system.
Early implementations of the various power modes required the computer hardware itself to monitor user activity and determine the proper power state for each device in the computer system. These early computer systems included a read only memory (ROM) device that stored a set of instructions for the computer to follow in order to carry out power management functions. The set of instructions formed part of the Basic Input/Output System (BIOS) of the computer, which also included instructions for procedures such as accessing data on a hard or floppy disk drive and controlling the graphics display. The ROM device containing the BIOS is referred to as the xe2x80x9cBIOS ROM.xe2x80x9d Because hardware-based power management instructions usually are included in BIOS, such a management scheme is commonly known as xe2x80x9cBIOS power management.xe2x80x9d Under BIOS power management, conditions within the computer system that initiate power state transitions, such as button presses and periods of inactivity explained above, generate system management interrupt (SMI) signals to the central processing unit (CPU). Upon receiving an SMI, the CPU executes the BIOS power management instructions stored in ROM to change the power state.
More recently, the Advanced Configuration and Power Interface (ACPI) specification, written collaboratively by Intel, Microsoft, and Toshiba, has introduced the concept of managing power functions using the computer""s operating system software (e.g., Windows(copyright) 98 and Windows(copyright) NT). Centralizing power management within the operating system, in contrast with earlier hardware-based power management techniques, allows computer manufacturers to make simpler, less expensive hardware components that do not have to manage their own power states. Instead, these devices need only to respond to power management commands from the operating system. In general, operating system-based power management enables the computer system to implement relatively complex power management procedures that may have been difficult, if not impossible, to realize using a more decentralized, hardware-based approach. In fact, implementing power control through ACPI, instead of through traditional hardware methods, can significantly reduce the power consumption of some computer systems. Operating system-based power management also provides the user with some level of power management control.
Under ACPI, a computer system can operate in one of six system power states, S0, S1, S2, S3, S4, and S5, which encompass varying levels of system activity ranging from fully operational (S0) to xe2x80x9csoft offxe2x80x9d (S5). Power states S1-S5 represent sleeping states, in which the computer system is neither fully operational nor completely powered off. The sleep states generally encompass varying levels of system activity (or xe2x80x9ccontextxe2x80x9d) and require different lengths of time (or xe2x80x9cwakeup latenciesxe2x80x9d) to return to full power. Because sleep state S5 represents the deepest sleep state, it may also be referred to equivalently as the xe2x80x9coffxe2x80x9d state or as the lowest-power state.
Transitioning between the system power states generally requires cooperation between the operating system and the computer hardware. The computer provides a set of ACPI registers which the operating system can access. To transition to one of the sleep modes from full-power mode (S0), the operating system stores special sleep codes into a pair of ACPI control registers. The control registers are known as the PM1a and PM1b Control Registers, and each sleep code includes a sleep enable bit and three sleep-type bits. The sleep-type bits generally identify one of the power states S1-S5. Upon detecting that the operating system has set (or xe2x80x9cassertedxe2x80x9d) the sleep enable bit, the computer places itself into a sleep mode as defined by the sleep-type bits.
As stated above, the operating system may direct the hardware to place itself into a sleep mode for a variety of reasons. For example, the computer hardware may provide a timer that expires after a predetermined time of inactivity within the system, prompting the OS to place a sleep request into the sleep-type and sleep enable bits of the control register. Alternatively, the operating system may write a sleep request to the control register after detecting that the user has initiated a sleep mode through the software interface, pressed sleep button on the computer chassis, or simply closed the computer screen (e.g., on a laptop computer). When the sleep enable bit of the control register is asserted, the computer system places itself into the low-power mode indicated by the value of the sleep-type bits.
The ACPI protocol also includes a status register to enable system wakeup. The status register, known as the PM1 Status Register, includes a wake status bit. The wake status bit typically is set if the user presses a wakeup button or power button on the computer. Certain devices in the computer system, such as the modem or network interface card (NIC), also may cause the wake status bit to be set in response to incoming messages (e.g., phone rings or network xe2x80x9cwakeupxe2x80x9d messages). When the operating system detects that the wake status bit has been set, the operating system transitions computer operation to the S0 mode.
To more clearly illustrate transitions between the power modes, FIG. 1 shows a representative conventional computer system that generally includes a CPU, a main memory array, and a bridge logic device coupling the CPU and main memory. The bridge logic device is sometimes referred to as a xe2x80x9cNorth bridgexe2x80x9d for no other reason than it often is depicted at the upper end of a computer system drawing. The North bridge couples the CPU and memory to the peripheral devices in the system through a Peripheral Component Interconnect (PCI) bus or other expansion bus, such as an Extended Industry Standard Architecture (EISA) bus. Various peripheral devices that implement the PCI protocol may reside on the PCI bus, as well. For example, a modem and network interface card (NIC) are shown coupled to the PCI bus in FIG. 1. The modem generally allows the computer to communicate with other computers over a telephone line, an Integrated Services Digital Network (ISDN), or a cable television connection, while the NIC permits communication between computers over a local area network (LAN) (e.g., an Ethernet network). The North bridge logic also may provide an interface to an Advanced Graphics Protocol (AGP) bus that supports a graphics controller to drive a video display. If the computer system does not include an AGP bus, the graphics controller may reside on the PCI bus.
If other secondary expansion buses are provided in the computer system, another bridge logic device typically couples the PCI bus to that expansion bus. This bridge logic is sometimes referred to as a xe2x80x9cSouth bridge,xe2x80x9d reflecting its location vis-à-vis the North bridge in a typical computer system drawing. In FIG. 1, the South bridge couples the PCI bus to an Industry Standard Architecture (ISA) bus and to an Integrated Drive Electronics (IDE) bus. The IDE bus typically interfaces input and output devices such as a CD ROM drive, a Digital Video Disk (DVD) drive, a hard disk drive, and one or more floppy disk drives. Various ISA-compatible devices are shown coupled to the ISA bus, including a BIOS ROM. As noted above, the BIOS ROM is a memory device that stores commands that instruct the computer how to perform basic functions such as sending video data to the display or accessing data on hard and floppy disk drives. In addition, the BIOS ROM may be used to store power management instructions for hardware-based (or xe2x80x9clegacyxe2x80x9d) power management systems. The BIOS instructions also enable the computer to load the operating system software program into main memory during system initialization, also known as the xe2x80x9cbootxe2x80x9d sequence. The BIOS ROM typically is a xe2x80x9cnonvolatilexe2x80x9d memory device, which means that the memory contents remain intact even when the computer powers down. By contrast, the contents of the main memory typically are xe2x80x9cvolatilexe2x80x9d and thus are lost when the computer shuts down.
The South bridge may also support an input/output (I/O) controller that interfaces to basic input/output devices (not shown) such as a keyboard, a mouse, a floppy disk drive, and various input switches such as a power switch and a sleep switch. The I/O controller typically couples to the South bridge via a standard bus, shown as an ISA bus in FIG. 1. A serial bus, which generally is a bus with only one data signal, may provide an additional connection between the I/O controller and South bridge. The I/O controller typically includes an ISA bus interface (not specifically shown) and transmit and receive registers (not specifically shown) for exchanging data with the South bridge over the serial bus.
Under hardware-based power control, the I/O controller generally handles some power management functions such as reducing or terminating power to components such as the floppy drive (not shown), gating the clock signals that drive components such as the bridge devices and CPU, and initiating sleep mode transitions on the peripheral buses. The I/O controller further asserts SMI signals (not shown) to the CPU in response to certain input signals, for example a signal from the power button to wake the computer from sleep mode. The I/O controller typically incorporates a counter or a Real Time Clock (RTC) to track the activities of certain components such as the hard drive and the PCI bus, inducing sleep mode after a predetermined time of inactivity.
Under the ACPI protocol, however, the South bridge or other component within the computer system typically manages power functions under the direction of the operating system. In the system illustrated in FIG. 1, for example, the South bridge provides a STOP GRANT signal to the CPU capable of halting CPU operation. Accordingly, the South bridge may assert the STOP GRANT signal when placing the computer into a sleep mode. The BIOS ROM stores the address locations of the ACPI registers in tabular form, and the operating system reads the ACPI table from the BIOS ROM during the computer boot sequence. The South bridge may contain some, or all, of the ACPI registers. For example, the BIOS ROM may define the PM1 Status and Control Registers as registers within the South bridge. Thereafter, the operating system uses these registers for ACPI power management. To place the computer in sleep mode, for instance, the operating system writes a sleep message to the PM1a and PM1b Control Registers. One or both of these registers may reside in the South bridge. As explained above, the sleep messages include sleep codes identifying one of the sleep modes (S1-S5) for the sleep-type bits and logical xe2x80x9conexe2x80x9d values for the sleep enable bits to trigger a change to sleep mode. The ACPI table defines the sleep codes for the PM1a and PM1b registers, and the sleep codes for the PM1a register are defined independently of the sleep codes for the PM1b register. Upon detecting that the operating system has set the sleep enable bit, the South bridge immediately places the computer system into the appropriate sleep mode. When a wakeup event occurs, the South bridge wakes the computer system, sets the wake status bit in the PM1 Status Register, and transmits a system control interrupt (SCI) to notify the operating system that fall-power mode has resumed.
Even while the computer is in sleep mode, it may be desirable to maintain just enough activity in the modem and/or NIC to allow these devices to monitor for incoming messages and wake the computer when necessary. For instance, some computers include voice mail, fax, and/or remote communications software programs that answer incoming telephone calls. While the computer is asleep, the modem must be able to monitor the telephone line and wake up the computer if the phone line rings. The computer can then answer the phone call. Similarly, the NIC occasionally may receive xe2x80x9cwakeupxe2x80x9d messages over the network, such as when a remote user attempts to access the sleeping computer. If the NIC detects such a message, it should be capable of waking the computer to respond to the message. Accordingly, the modem or NIC may command the South bridge to bring the computer out of sleep mode and set the wake status bit.
Providing peripheral devices such as a modem or NIC with the capability to monitor for incoming messages while the computer is asleep and to wake the computer system when necessary, however, can create numerous difficulties if the peripheral devices are not designed to comply with the ACPI protocol. Typically, these peripheral devices, which are referred to as xe2x80x9clegacyxe2x80x9d peripheral devices, require special configuration sequences before sleep mode begins in order to begin monitoring for incoming communications. If a legacy device is simply placed into sleep mode without the proper configuration sequence, then the device may not be capable of detecting incoming messages. ACPI requires the operating system to prepare for sleep mode before the sleep enable bit is set, however, and with operating system resources prepared for sleep mode after setting the sleep enable bit, no operating system routines are available to perform the necessary legacy device configuration sequences. Thus, legacy peripheral devices operating under ACPI cannot return the computer system to full-power mode in response to incoming wakeup messages, since prior to entering sleep mode, the OS was not able to configure the devices. As a consequence, computer users that rely on these legacy peripheral devices may not be able to successfully upgrade to future computer systems that use ACPI power management.
For the foregoing reasons, an ACPI-compliant computer system that can configure legacy devices for sleep mode after the operating system initiates a sleep mode would greatly improve computer system operation. Despite the apparent advantages that such a system would provide, to date, no such device has been developed that provides this feature.
Accordingly, the present invention discloses a computer system that is configured to implement a software-based power management system, thereby allowing more elaborate and efficient power management functions than were possible under hardware-based power management. At the same time, the computer system flexibly permits hardware-based configuration of legacy peripherals and other devices within the computer that are not configurable through software-based power management. Conventional computers running under the ACPI power management protocol include special control registers (i.e., the PM1a and PM1b Control Registers) that, when written to by the operating system, initiate the transition to a low-power mode in the computer system. The computer system of this disclosure incorporates a power management circuit that comprises a xe2x80x9cdecoyxe2x80x9d register, a xe2x80x9csleepxe2x80x9d register, interrupt generation circuitry, and circuitry to control the power state within the computer system.
The sleep register serves as the ACPI PM1a Control Register, and the decoy register serves as the ACPI PM1b Control Register. The decoy and sleep registers thus are constructed substantially according to the architecture of the PM1 Control Register as defined in the ACPI Specification, version 1.1, and incorporate the bit definitions of the PM1 Control Register including, in particular, the sleep enable bits and the sleep codes that comprise the ACPI sleep type bits. The computer system relies on the sleep register to determine the appropriate power state. Based on the power state, as defined by the sleep type bits in the sleep register, the power management circuit controls the computer system power mode. If the PM1a sleep enable bit is set, then the computer transitions to the power mode defined by the PM1a sleep type bits. Because the operating system writes to the PM1a and PM1b registers at the same time under ACPI, the decoy register (i.e., the PM1b register) receives sleep requests as well.
To allow the computer to configure peripheral devices before changing power states, the ACPI table in BIOS defines the sleep codes for the PM1a (sleep) register to have the same values. All of the PM1a sleep type codes are set to a value that represents a fully operating mode. In a preferred embodiment, the PM1a sleep codes represent the S0 code which represents the fully operational ACPI power state. As a result, sleep requests from the operating system write the S0 code into the sleep register, no matter which sleep state the operating system intended to request.
In contrast, the ACPI table defines the true sleep type codes for the PM1b (decoy) register, so that the decoy register receives sleep codes that represent the power state that the operating system actually intended to request. If the sleep request sets the PM1b sleep bit to initiate the sleep mode indicated by the PM1b sleep type bits, then the computer responds by configuring the peripheral devices for the appropriate sleep mode. Setting the sleep enable (SLP_EN) bit in the decoy register generates an SMI to notify the microprocessor that the operating system placed a sleep request. The sleep enable bit preferably is located in the highest byte of the decoy register so that an SMI is triggered only when data is written to the highest byte. Because the operating system may write data to the register in 8-bit segments, starting with the lowest byte of the register, placing the sleep enable bit in the highest register prevents 8-bit writes from initiating sleep mode before the entire data word (16 data bits) is written to the highest byte.
In response to the SMI generated from the decoy register, the central processing unit (CPU) of the computer executes an interrupt service routine to configure various peripheral devices for low-power operation. After configuring the peripheral devices, the CPU transfers the contents of the decoy register (PM1b ), including the true sleep code, into the sleep register (PM1a ). The sleep register preferably resides in a South bridge device that controls the ACPI power states of the computer system based on the sleep type code (i.e., the sleep type bits) stored in the sleep register. Hence, transferring the sleep request from the decoy register to the sleep register puts the true sleep code into the sleep register, causing the South bridge to place the computer into a sleep mode. Because the CPU configures the peripheral devices before the system enters sleep mode, the peripherals perform as intended even while asleep, even if the power management software cannot configure the devices. At the same time, the computer system fully compiles with power transition requests from the operating system, albeit after a slight delay.
Thus, the present invention comprises a combination of features and advantages that enable it to substantially advance the art by providing a computer system that complies with software-based power management while still permitting hardware-based power management of some devices within the system. These and various other characteristics and advantages of the present invention will be readily apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments of the invention and by referring to the accompanying drawings.